TSMC: Energy Efficiency Reshaping AI Chip Design

TSMC Executive: Energy Efficiency Now Top Priority

Kevin Zhang, Senior Vice President of Business Development at TSMC, said surging electricity demands from AI are making energy efficiency the main constraint shaping future chip development. Speaking at a conference in Amsterdam, Zhang noted that customers increasingly prioritize performance gains that do not drive up power use.

A Turning Point for the Semiconductor Industry

Zhang emphasized that energy efficiency is the most desired improvement across all sectors, from smartphones to AI data centers. This shift marks a turning point where simply packing more transistors onto chips is no longer sufficient for sustaining performance gains in energy-hungry AI workloads.

TSMC's Roadmap and Future Technologies

TSMC expects its chips to cut power consumption by up to 30% between its N2 technology and A14 generation, due around 2028, while delivering over 20% higher computing performance. Advanced packaging, chip stacking, and photonics are becoming increasingly important to boost efficiency.

Competitors and Alternative Approaches

Chinese rival Huawei unveiled its 'Tau Scaling Law' plan to improve performance by speeding up data movement within chips. Zhang described the concept as long-standing in the industry, largely dependent on integrating components more closely through 3D stacking. Huawei's approach reflects constraints faced by Chinese firms barred from accessing ASML's EUV lithography machines due to U.S.-led export controls.